1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to an erasure check operation to be performed when data stored in a flash EEPROM (Electrically Erasable Programmable Read Only Memory) is erased.
2. Description of the Related Art
FIG. 2 shows a conventional NOR type flash EEPROM. In this flash EEPROM, memory cells 10 respectively having floating gates are arranged in the form of a matrix. The control gates of the memory cells 10 are respectively connected to row lines WL1, WL2, WL3, . . . , WLi. The respective row lines WL1, WL2, WL3, . . . . WLi are connected to a row decoder 11. The sources of the memory cells 10 are connected to a power supply VE. The drains of the memory cells 10 are respectively connected to column lines CL1, CL2, CL3, . . . , CLn. The sources of n-channel transistors G1, G2, G3, . . . , Gn are connected to the column lines CL1, CL2, CL3, . . . , CLn, respectively. The gates of the transistors G1, G2, G3, . . . , Gn are connected to a column decoder 12. The drains of the transistors G1, G2, G3, . . . , Gn are connected to a high-voltage power supply Vp (12 V) through an n-channel transistor 13. The gate of the transistor 13 is connected to a data input circuit 14.
The drains of the transistors G1, G2, G3, . . . , Gn are connected to the source of an n-channel transistor 15 and are also connected to the gate of the transistor 15 through a feedback inverter circuit 16. The drain of the transistor 15 is connected to a sense amplifier (not shown) and is also connected to the gate and drain of a p-channel load transistor 17. The source of the load transistor 17 is connected to a power supply Vc.
In the above-described arrangement, when data is to be read out from a memory cell, one row line and one column line are selected from a plurality of row lines and a plurality of column lines by the row decoder 11 and the column decoder 12, respectively, and data is read out from the memory cell 10 located at the intersection between the selected row and column lines.
When the data stored in a memory cell 10 is to be erased, a high voltage VE is applied to the source of the memory cell 10 to emit electrons from the floating gate of the memory cell to its source.
When data is to be written in a memory cell 10, a high voltage from the power supply Vp is applied to the gate and drain of the memory cell 10, selected in the above-described manner, through the n-channel transistor 13 to cause a current to flow in the channel region of the memory cell 10 so as to generate electron-hole pairs, thus injecting electrons from the channel into the floating gate of the memory cell 10.
In a data erase operation in the above-described flash EEPROM, if an excessive amount of electrons are emitted from the floating gate of a memory cell, the threshold voltage of the memory cell becomes a negative value. Consequently, each non-selected memory cell whose gate voltage is set to 0 V is also rendered conductive, disabling a selecting operation. In the conventional EEPROM, therefore, erase and read operations are performed repeatedly, and the electron-emitted state of the floating gate is checked in each read operation so that erasure is stopped when the threshold voltage of the memory cell reaches a proper value. More specifically, the time required for one erase operation is set to be short to prevent a memory cell from having a negative threshold voltage after one erase operation, and the electron-emitted state of the floating gate is checked by reading out data from the memory cell after every data erasure. When the threshold voltage reaches a proper value, erasure is stopped.
As described above, in the conventional EEPROM, erase and read operations are performed repeatedly. In the read operation, all the memory cells are sequentially selected to read out data therefrom. Therefore, it takes much time to erase the data stored in a memory cell.
FIG. 3 shows a conventional flash EEPROM. The same reference numerals in FIG. 3 denote the same parts as in FIG. 2. The arrangement shown in FIG. 3 is different from that shown in FIG. 2 in that the source of an n-channel transistor 20 is connected to the drains of the transistors G1, G2, G3, . . . , Gn. The gate of the transistor 20 is connected to the output terminal of the inverter circuit 16. The drain of the transistor 20 is connected to the power supply Vc.
Similar to the flash EEPROM in FIG. 2, in the flash EEPROM shown in FIG. 3, the time required for one erase operation is set to be short to prevent a memory cell from having a negative threshold voltage after one erase operation, and the electron-emitted state of the floating gate is checked by reading out data from the memory cell after every data erasure. When the threshold voltage reaches a proper value, erasure is stopped.
The above-mentioned check operation is performed by using a sense amplifier 21 shown in FIG. 4. An input voltage Vin (corresponding to a current Icell flowing in a memory cell which has undergone data erasure) is applied to one input terminal of the sense amplifier 21, whereas a reference voltage vref (corresponding to a reference current Iref) output from a reference circuit 22 is applied to the other input terminal. The reference circuit 22 has the same arrangement as that of an equivalent portion on the memory cell side shown in FIG. 3. The same reference numerals each with suffix "a" in FIG. 4 denote the same parts as in FIG. 3. Note that reference numeral 10a denotes a dummy cell.
The sense amplifier 21 compares the input voltage Vin with the reference voltage Vref output from the reference circuit 22. If the input voltage Vin is lower than the reference voltage Vref, data erasure of the memory cell is completed.
The degree to which the current Icell flowing in a memory cell increases, as a criterion for determining completion of data erasure, can be determined by the ratio of the current supply capacity of the load transistor 17 on the memory cell side to that of a load transistor 17a of the reference circuit 22. Assume that a pair of transistors 21a and 21b, and a pair of transistors 22c and 22d constituting the sense amplifier 21 have the same dimensions, respectively, and that the current supply capacity of the load transistor 17 on the memory cell side is half that of the load transistor 17a of the reference circuit 22. In this case, when the current Icell increases to nearly half of the reference current Iref, completion of data erasure is determined.
A data erase operation must be carefully performed to prevent a memory cell from having a negative threshold voltage after excessively emitting electrons from its floating gate. For this reason, setting of the currents Icell and Iref is important. As the difference in potential between Vin and Vref increases, determination can be more accurately performed by the sense amplifier 21. That is, the setting of Icell and Iref may be performed such that a great change in Vin is caused by a slight change in Icell, and a great change in the potential difference between Vin and Vref is caused by a slight change in Icell. In the conventional circuit shown in FIG. 3, the transistors 20 and 15 are controlled by the feedback inverter circuit 16 whose input terminal is connected to a column line. This arrangement is designed to increase the data read speed by reducing the amplitude of the potential of a column line. The transistor 15 amplifies the small potential amplitude of the column line and transfers it, as the input voltage Vin, to the sense amplifier 21. When an output from the column decoder 12 changes to select a new column line, the transistor 20 is used to rapidly charge the selected column line from 0 V.
In the conventional circuit shown in FIG. 3, since the two transistors 20 and 17 serve as loads with respect to a memory cell, when a current flows in the memory cell, currents also flow in the load transistors 20 and 17. The sense amplifier 21 checks an erased state on the basis of currents flowing in the transistors 21a and 21b. For this reason, a current component flowing in the load transistor 17 cannot be accurately checked as a current flowing in the memory cell itself. As the data in the memory cell is erased and the current flowing in the memory cell itself increases, the current flowing in the load transistor 20 increases, resulting in an increase in error.
As the current flowing in the memory cell itself increases in the process of data erasure, the current is also compensated by the transistor 20. Therefore, a change in Vin is small as compared with an increase in current flowing in the memory cell itself.
As described above, in the conventional circuit shown in FIG. 3, a change in Vin is small as compared with an increase in current flowing in a memory cell itself, and the current flowing in the memory cell itself cannot be accurately monitored.
As described above, in data erasure of the flash EEPROM shown in FIG. 2, the time required for one erase operation is set to be short to prevent a memory cell from having a negative threshold voltage after one erase operation, and the electron-emitted state of the floating gate is checked by reading out data from the memory cell after every data erasure. When the threshold voltage reaches a proper value, erasure is stopped.
In erasing the data stored in a memory cell, the erase time varies depending on the amount of electrons in the floating gate at the start time of data erasure. For this reason, in order to reduce variations in the threshold voltages of the erased memory cells, data erasure is performed after data are written in all the memory cells. That is, an erase operation is performed after electrons are injected into the floating gates of all the memory cells.
Even if, however, an erase operation is performed by such a method, the threshold voltages of all the memory cells after the erase operation do not become uniform and vary according to a certain distribution owing to subtle variations in the quality of a gate oxide film and a manufacturing process. As described above, this distribution is formed because of subtle variations in the quality of a gate oxide film and a manufacturing process. The threshold voltages of the respective memory cells differ in units of the manufacturing lots.
FIGS. 5A and 5B show variations in the threshold voltages (Vth) of memory cells after data erasure in units of lots. The threshold voltages of memory cells vary in various ranges, e.g., a narrow range such as the one shown in FIG. 5A and a wide range such as the one shown in FIG. 5B.
The electron-emitted state of a floating gate is checked by reading data from the memory cell. In this check, completion of data erasure is determined by detecting whether the potential of the column line is lower than a predetermined potential. As described above, this read operation is performed by a sense amplifier and the like. If the potential of the column line is lower than a predetermined reference voltage, it is determined that the erase operation is completed. Although the threshold voltage of a memory cell which has undergone data erasure must not be a negative value, a lower threshold voltage is better in the interest of increasing the read speed by increasing a current flowing in the memory cell.
In the conventional memory devices, even with a lot having a wide distribution of threshold voltages as shown in FIG. 5B, a reference potential is determined such that the threshold voltage of a memory cell does not become a negative value after an erase operation. For this reason, as shown in FIG. 5C, a threshold voltage Vth1 of the lot shown in FIG. 5B is applied to even a lot having a narrow distribution of threshold voltages after data erasure, which exhibits a wide margin on the 0-V side as in FIG. 5A. In the conventional memory devices, a high threshold voltage is set for each memory cell regardless of whether the distribution of threshold voltages is narrow, and a lower threshold voltage can be set for each memory cell to allow an increase in data read speed. That is, the conventional memory devices are not suitable for a high-speed operation.
In the flash EEPROM shown in FIG. 2, data erasure is performed, after data is written in each memory cell (electrons are injected into the floating gates of all the memory cells.) This data writing operation is the same as a normal writing operation of a normal writing mode. For this reason, it takes much time to erase the data stored in a memory cell. That is, in the conventional memory devices, a data erase operation requires the sum of the time required to emit electrons from the floating gates of memory cells and the time required to write data.